FIG. 1 shows a typical active matrix display. Such a display is made up of a matrix 2 of picture elements (pixels), arranged in M and N columns. Each row and column is connected to an electrode, with the column electrodes being connected to the N outputs of a data driver 4 and the row electrodes being connected to the M outputs of a scan driver 6.
The pixels are addressed one row at a time. The scan driver includes an M-phase clock generator, which produces a series of clock pulses as shown in FIG. 2. Each clock phase OUTi controls the activation of row i. It is usual for the pulses to be non-overlapping, such that no two pulses are high at the same time.
All the pixels of one row may be addressed simultaneously, or they may be addressed in B blocks of b pixels, where bB=N. In the latter case, the data driver may also include a B-phase clock generator of the type described, such that each clock pulse OUTi activates block i.
Normal operation of the display is such that data is sampled onto the pixels from top to bottom and from left to right, corresponding to the timing shown in FIG. 2. However, it is a common requirement for the direction of sampling to be switchable, such that data is sampled onto the pixels from the bottom to top and/or from right to left. In this way, it is possible to reflect or rotate the displayed image without re-ordering the input data. Such re-ordering requires considerable additional circuitry, such as additional memory sufficient to store the whole image.
In this case, the clock generators must in addition be able to operate bi-directionally, producing either clock pulses as in FIG. 2, or clock pulses of the type shown in FIG. 3. Each pulse OUT in FIG. 3 still activates row i. However, pulse OUTi occurs before pulse OUTi−1, whereas in FIG. 2 pulse OUTi occurred after pulse OUTi−1.
Clock generators of the type described may be formed directly on the display substrate, reducing the number of connections required to the display. This is advantageous, since it reduces the area occupied by the connector, and leads to a display which is more mechanically robust.
Such a clock generator may be formed from a shift register. A shift register is a multi-stage circuit capable of sequentially shifting a sequence of data from stage to stage along its length in response to a clock signal. In general, a shift register may shift an arbitrary sequence of data. However, when a shift register is used as a clock generator in a scan or data driver, it is only required to shift a single high state along its length. Such a shift register is referred to as a “walking one” shift register, and may or may not be capable of shifting an arbitrary sequence of data.
A known type of clock generator for use in such an application is a shift register comprised of a cascade of D-type flip-flops (DFF) 12 controlled by a clock signal CK, as shown in FIG. 4. On each rising edge of CK, the data at the Q output of DFF 12i is sampled onto the D input of DFF 12i+1, and is passed to its Q output. In this way, data can be passed along the register one stage at a time. It can be seen that, if a single ‘1’ is sampled onto the D input of the first DFF 12l, the outputs of the register, Qi, will be of the general form shown in FIG. 2.
However, this type of shift register has two disadvantages when it is required to generate pulses for use in a scan driver: first, that the pulses have coincident edges (that is Qi+1 rises as Qi falls); and second, that there is no simple method to reverse its direction of scan. In order to control the time between Qi falling and Qi+1 rising, it is necessary to include an additional circuit element or elements between the respective stages. To control the direction of scan it is necessary to include switches such that Qi may be connected to either Di−1 or Di+1. Such additional elements and switches add to the area required for the circuit, and require additional control signals (in general a switch is made up of an n-channel and a p-channel transistor, and requires both a control signal UD and its complement UDB to control its conduction). In particular, it is desirable to remove the switches since they and their associated wiring occupy a larger physical area than a similar number of logic transistors.
An example of such a clock generator is disclosed in U.S. Pat. No. 5,282,234, and is shown in FIG. 5. In this case, the shift register is composed of a series of flip-flops 14 with additional elements to prevent coincident edges (an analogue switch, an inverter with hysteresis and a capacitor), and a set of switches 16-22 to control the direction of propagation.
Another example of such a type of clock generator is disclosed in U.S. Pat. No. 6,377,099, and is shown in FIG. 6. In this case, the flip-flop 24 is of the reset-set type (RSFF), with an additional gate 26 to control the passage of the clock. The output of gate 26 sets the next RSFF 24i+1 and resets the previous RSFF 24i−1. In order for this shift register to operate bi-directionally, switches are required to connect the output of the gate 26i to the set input of RSFF 24i−1 or 24i+1, and to the reset input of RSFF 24i+1 or 24i−1.
An alternative type of shift register is disclosed in the US patent application 2004/015061A1, and is shown in FIG. 7. This type of register is composed of a cascade of RSFFs 25, but does not require switches to operate bi-directionally. However, the register requires at least three clock signals, and, since its outputs are overlapping, it requires additional logic and/or signals to generate non-overlapping output pulses. The additional clocks increase the complexity of the circuits controlling the register, and, in the case where the register is formed on the display substrate, increase the number of connections to the display.
All of the above registers are started by a start pulse generator applied to one end of the register. Their direction of scan is controlled by the combination of the choice of start point and either the order of the clocks, or by an additional signal or signals.